This invention relates to the field of integrated circuits, and more specifically to programmable logic devices.
Programmable logic devices (PLDs) are a class of integrated circuits (ICs) that can be programmed by a user to emulate various logic functions. Logic designers typically use PLDs to implement control logic in electronic systems because they are relatively easy to program, and often can be reprogrammed to update the emulated logic function. This often makes the use of PLDs less costly in comparison to custom hardwired or xe2x80x9capplication specificxe2x80x9d integrated circuits (ASICs).
PLDs include configurable (programmable) logic resources that are controlled by configuration data stored in configuration memory cells on the PLD. PLD configuration memory is typically classified as either non-volatile (e.g., EPROM, EEPROM, or flash and/or fuse/antifuse), or volatile (e.g., SRAM). The benefit of non-volatile memory is that configuration data is retained (persistent) even if power is discontinued. However, non-volatile memory typically requires special programming and erasing voltages, and typically requires relatively long program/erase times. In contrast, volatile memory (e.g., SRAM memory) is readily configured using normal system voltages, but requires a configuration operation (i.e., writing configuration data into the volatile memory array) each time power to the PLD is terminated.
Configuration operations typically involve transmitting configuration data values from a non-volatile memory device (e.g., an EPROM) to the volatile configuration memory of a PLD. However, some recently developed PLDs include both a non-volatile memory array and volatile memory array on the same chip. At power-up, the configuration data is written from the non-volatile memory array to the volatile memory array, which then controls programmable logic of the PLD during normal operation.
A potential problem with PLDs utilizing volatile configuration memory is the potential storage of erroneous configuration data in the volatile memory array. These storage errors occur, for example, at power-up because configuration data is written to the volatile memory array before system voltages have stabilized, thereby causing one or more volatile memory cells to store erroneous data values. Accordingly, when normal operations are initiated, the PLD can implement an unintended logic operation.
What is needed is a circuit and method for verifying that a PLD is properly configured before initiating a user""s logic function.
The present invention is directed to a circuit and a method for verifying that configuration data is successfully transferred to a volatile memory array in a PLD.
According to the present invention, configuration data is verified during each stage of a configuration operation by comparing a set of configuration data values transmitted on a series of write lines to stored data values read from a column of volatile configuration memory cells of the PLD. The configuration operation is controlled such that sequential groups of configuration data values are transmitted onto the write lines when a preceding group of configuration data values are successfully stored in an addressed group of volatile memory cells. Specifically, when a group of configuration data values are transmitted on the write lines, each volatile memory cell is addressed (a) to latch a configuration data value transmitted on a corresponding write line, and (b) to transfer the currently stored data value onto a corresponding read line. When the configuration data value transmitted on each write line is equal to the stored data value transmitted on each corresponding read line, the comparator generates a control signal verifying that the configuration data values are successfully stored in the volatile memory cells. The control signal is then used to control the transmission of a new set of configuration data values and to address a new set of volatile memory cells.
In accordance with the present invention, a PLD includes an addressing circuit and a comparator circuit to control the transfer of configuration data from a non-volatile memory array to a volatile memory array. The addressing circuit generates an address signal that is applied to a selected column of non-volatile memory cells, causing the column of non-volatile memory cells to transmit configuration data values onto a series of write lines. The address signal is also applied to first select transistors of a corresponding column of volatile memory cells, thereby selectively coupling each volatile memory cell to a corresponding write line. In addition, the address signal is applied to second select transistors of the corresponding column of volatile memory cells, thereby causing each volatile memory cell to transmit its stored data value onto a corresponding read line. The comparator circuit compares the configuration data value on each write line with the stored data value transmitted from the associated volatile memory cell on the corresponding read line, and generates a control signal only when all of the configuration data values match the stored data values. This control signal is used to increment the addressing circuit, thereby causing a second column of non-volatile memory cells to write configuration data values on the write lines to a corresponding second column of volatile memory cells, whose stored data values are then compared in the manner described above. This process is repeated until all configuration data values are written to the volatile memory array. After the configuration operation is completed, the programmable logic resources are controlled by the volatile memory array to perform a user""s logic operation that is defined by the configuration data.
The present invention prevents incrementing the addressing circuit until the data values stored in all of the volatile memory cells are equal to the configuration data values transmitted to the volatile memory cells. Accordingly, the present invention avoids erroneous configuration of the volatile memory cells due, for example, to a fluctuating voltage supply at power-up, by delaying the configuration operation until the voltage supply is sufficiently stabilized to successfully transfer all configuration data values to the volatile memory array.